In recent years, the spread of flat panel type display devices as monitors and displays of personal computers and video equipment has been remarkable. Particularly, Liquid Crystal Displays (hereinafter denoted as “LCD”) have many advantages as these devices are thin-shaped, space-saving, low-powered and the like as compared to conventional display devices.
Furthermore, as the next-generation display device technology which supplants current LCD's, Research and Development (R&D) of a self-luminescence type display devices (self-luminescence type displays) equipped with a display panel which performs two-dimensional digital array of the display pixels is being actively developed. These LCD's comprise a self-luminescence type display device composed of light emitting devices to perform luminescent operation according to the display data and extensively employ organic electroluminescent devices (hereinafter denoted as “organic EL devices”) or Light Emitting Diodes (LEDs) and the like.
Such self-luminescence type displays as compared to LCD's have rapid display response speed to moving images and there is no angle-of-visibility dependability. Additionally, because backlight is not needed like an LCD, higher luminance with a greater contrast ratio, higher resolution of the display image quality together with using low-power are attainable. These very predominant features will lead to extremely thin-shaped and lightweight models and full-scale utilization of such self-luminescence type displays are expected in the near future.
In self-luminescence type display configurations which apply an active-matrix drive method, various drive control mechanisms and control methods of the display pixels comprising a display device composed of light emitting devices constituted of a plurality of switching elements for controlling operation of the light emitting devices have been proposed.
FIGS. 15A and 15B are equivalent circuit drawings showing prior art example configurations as in the case of the display pixels applied to organic EL devices OEL as the light emitting devices in a self-luminescence type display.
The configuration shown in FIG. 15A comprises a voltage application method which is constituted with a light generation driver circuit DP1 comprising an n-channel type Thin-Film Transistor (TFT) Tr111, a p-channel type Thin-Film Transistor Tr112, a capacitor CP1 and the organic EL devices OEL. The light generation driver circuit DP1 comprises the n-channel type Thin-Film Transistor (TFT) Tr111 (hereinafter denoted as “Nch transistor”) whereby the gate terminal is connected to the scanning lines SL, along with the source terminal and the drain terminal each other connected to the data lines DL and the contact point N111 (hereinafter denoted as “contact” for the convenience of explanation) each near the intersecting point of a plurality of scanning lines SL and data lines DL arranged in matrix form in the display panel; the capacitor CP1 gate terminal is connected to contact N111 which is connected in between the p-channel type Thin-Film Transistor Tr112 (hereinafter denoted as “Pch transistor”) source terminal by which ground potential Vgnd is applied along with the contact N111 and the Pch transistor Tr112 gate terminal; and the organic EL devices OEL whereby the anode terminal is connected to the drain terminal of the Pch transistor Tr112 of the light generation driver circuit DP1 and the low power supply voltage Vss of low electric potential is applied to the cathode terminal lower than the ground potential Vgnd.
In this configuration, the gradation signal voltage Vpix according to the display data is applied to the data lines DL. When a high-level scanning signal Vsel is applied to the scanning lines SL and the display pixels are set to a selection state, the Nch transistor Tr111 in the light generation driver circuit DP1 performs an “ON” operation. The gradation signal voltage Vpix is applied to the data lines DL via Nch transistor Tr111 to the contact N111, specifically the gate terminal of Pch transistor Tr112. Accordingly, the Pch transistor Tr112 performs an “ON” operation by the switch-on state according to the above-mentioned gradation signal voltage Vpix and predetermined light generation drive current flows to the low voltage Vss via the Pch transistor Tr112 and the organic EL devices OEL from the ground potential Vgnd. Thus, the organic EL devices OEL perform luminescent operation by the luminosity gradation according to the above-mentioned display data. Subsequently, when a low-level scanning signal Vsel is applied to the scanning lines SL and the display pixels are set to a non-selection state, the Nch transistor Tr111 performs an “OFF” operation. Although the data lines DL and the light generation driver circuit DP1 are electrically blocked out, the voltage applied to the gate terminal of Pch transistor Tr112 is stored by the capacitor CP1 (parasitic capacitance) and one frame periods are performed.
Additionally, the configuration shown in FIG. 15B comprises a current application method which is constituted with the light generation circuit DP2 comprising an Nch transistor Tr121, Pch transistors Tr122 to Tr124, a capacitor CP2 and the organic EL devices OEL. The light generation circuit DP2 comprises the Nch transistor Tr121 gate is connected to first scanning lines SL1, along with the source terminal and drain terminal each other connected to the data lines DL and the contact N121 near the intersecting point of the first and second scanning lines SL1 and SL2 arranged in parallel to each other and the data lines DL; the Pch transistor Tr122 gate terminal is connected to the second scanning lines SL2, along with the source terminal and drain terminal each other connected to the contact N121 and contact N122; the Pch transistor Tr123 gate terminal is connected to the contact N122, along with the drain terminal each other connected to the contact N121 and the high voltage Vdd applied to the source terminal; the Pch transistor Tr124 gate terminal is connected to the contact N122 and the high voltage Vdd is applied to the source terminal; the capacitor CP2 is connected between the gate-source of the Pch transistors Tr123 and Tr124; and the organic EL devices OEL in which the anode terminal is connected to the drain terminal of Pch transistor Tr124 and the ground potential is applied to the cathode terminal.
In this configuration, the gradation current Ipix according to the display data is applied to the data lines DL. When the high-level scanning signal Vsel1 to the scanning lines SL1 and the low-level scanning signal Vsel2 to the scanning lines SL2 are each other applied and the display pixels are set to the selection state, the transistors Tr121 and Tr122 in the light generation driver circuit DP2 perform an “ON” operation. While the gradation current Ipix according to the display data applied to the data lines DL is taken in at the contact N122 via the transistors Tr121 and Tr122, the current level of this gradation current Ipix is converted to the voltage level by the Pch transistor Tr123 and predetermined voltage is generated between the gate-source. Subsequently, when the high-level scanning signal Vsel2 is applied to the scanning lines SL2, the Pch transistor Tr122 performs an “OFF” operation. The voltage generated between the gate-source of the Pch transistor Tr123 is stored by the capacitor CP2 (parasitic capacitance). Next, when the low-level scanning signal Vsel1 is applied to the scanning lines SL1, the Nch transistor Tr121 performs an “OFF” operation. The data lines DL and the light generation driver circuit DP2 are electrically blocked out and the Pch transistor performs an “ON” operation according to the electric potential difference based on the voltage stored in the above-mentioned capacitor CP2. As a result, predetermined light generation drive current from the high power supply voltage Vdd flows to ground potential via the Pch transistor Tr124 and the organic EL devices OEL, which is controlled so that the organic EL devices OEL emit light by the luminosity gradation according to the display data and one frame periods are performed.
Although the pixel driver circuit of the current application method as shown in the above-mentioned FIG. 15B has the advantage of not be being easily influenced by the effects of fluctuation or varying operating characteristics of each of the Thin-Film Transistors in the light generation driver circuit as opposed to the voltage application method as shown in FIG. 15A, there is an inherent problem with regard to writing gradation currents to each of the display pixels at the time of low gradation with comparatively low luminosity.
Accordingly, although it is necessary to supply and write-in gradation current to each of the display pixels which has a relatively low current value at the time of low luminosity gradation, the operation which writes in gradation currents in the display pixels is equivalent to charging the capacity component, such as the wiring capacitor and the like, which is parasitic on the data lines to predetermined voltage. For example, in the case where the wire length of the data lines is designed to be lengthened by enlargement of the display panel and the like, or the number of scanning lines are increased and high resolution is performed. Therefore, when the selection period of each of the scanning lines is set briefly to the extent that the current value of the gradation currents becomes low, the charging time period of the data lines requires more time and the time period required for the write-in operation to the display pixels becomes longer. Furthermore, by using the write-in time set beforehand, the pixels become written insufficiently and luminosity differences occur within the display panel.
FIG. 16 is the simulation results for illustrating the influence of the write-in characteristics on the display data in various types of display panels.
FIG. 17 is the simulation results for illustrating the influence of the write-in characteristics on the wiring capacitor in various types of display panels.
Here, the simulation results shown in FIGS. 16 and 17, illustrated in FIG. 16 as Sa˜Se, the size, the number of pixels and the like of the display panels, as well as the write-in rate of the display data in five types of displays which have respectively different specifications are shown.
The inclination of the write-in rate of the display data in low gradation drops significantly and the resultant write-in deficiency is shown as the display panel is enlarged the number of display pixels increases. In FIG. 16 as illustrated in each of the characteristic curves Sa-Se, shown is the correlation of the write-in rate to the gradation (write-in gradation) of the display data.
In addition, the inclination of the write-in rate of the display data drops significantly and the resultant write-in deficiency is shown as the display panel is enlarged the wire length of the data lines becomes longer and the distance from the data driver becomes lengthier. In FIG. 17 as illustrated in each of the characteristic curves Sa˜Se, shown is the correlation of the write-in rate to the arrangement position of the display pixels on the display panel.